Maurer computers for pipelined instruction processing
نویسندگان
چکیده
Maurer computers for pipelined instruction processing† J. A. BERGSTRA‡ and C. A. MIDDELBURG§ ‡Programming Research Group, University of Amsterdam, P.O. Box 41882, 1009 DB Amsterdam, the Netherlands and Department of Philosophy, Utrecht University, P.O. Box 80126, 3508 TC Utrecht, the Netherlands Email: [email protected] §Programming Research Group, University of Amsterdam, P.O. Box 41882, 1009 DB Amsterdam, the Netherlands Email: [email protected]
منابع مشابه
Implementing Precise Interrupts in Pipelined Processors
This paper describes and evaluates solutions to the precise interrupt problem in pipelined processors. An interrupt is precise if the saved process state corresponds with a sequential model of program execution where one instruction completes before the next begins. In a pipelined processor, precise interrupts are difficult to implement because an instruction may be initiated before its predece...
متن کاملReducing Branch Delay to Zero in Pipelined Processors
A mechanism to reduce the cost of branches in pipelined processors is described and evaluated. It is based on the use of multiple prefetch, early computation of the target address, delayed branch, and parallel execution of branches. The implementation of this mechanism using a Branch Target Instruction Memory is described. An analytical model of the performance of this implementation is present...
متن کاملOn Transformations of Load-Store Maurer Instruction Set Architectures
Maurer proposes a model for computers from the viewpoint of general function and set theory in [W.D66, W.D06]. Mathematical machines (Turing machines, push-down automata, etc.) are widely known for their inadequate representation of modern computers, but Maurer’s model gives a leading solution. Maurer machines [JC07a], introduced by Bergstra and Middelburg, are based on this model and basic thr...
متن کاملA Branch Instruction Processor for SCISM Organizations
The performance degradation caused by branch instructions in pipelined computers is well known. The degradation is even greater on computers with multiple pipelines processing a single instruction stream, such as superscalar and scalable compound instruction-set machines (SCISM). Several branch prediction schemes have been proposed that attempt to reduce this performance penalty. One of these {...
متن کاملOn Transformations of Load-Store Maurer Instruction Set Architecture
Maurer proposes a model for computers from the viewpoint of general function and set theory in [7, 8]. Mathematical machines (Turing machines, push-down automata, etc.) are widely known for their inadequate representation of modern computers, but Maurer’s model gives a leading solution. Maurer machines [1], introduced by Bergstra and Middelburg, are based on this model and basic thread algebra ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
- Mathematical Structures in Computer Science
دوره 18 شماره
صفحات -
تاریخ انتشار 2008